標題: | Cost-Effective Time-to-Digital Converter Using Time-Residue Feedback |
作者: | Lai, Jung-Chin Hsu, Terng-Yin 資訊工程學系 Department of Computer Science |
關鍵字: | Cyclic-ring Vernier;feedback;time amplifier (TA);time residue;time-to-digital converter (TDC) |
公開日期: | 1-六月-2017 |
摘要: | This paper proposes a time-residue feedback scheme to balance resolution and complexity in a cell-based time-to-digital converter (TDC). The time residue is amplified and fed back into a cyclic-ring Vernier recursively until it cannot be detected correctly. Only one variable-resolution cyclic-ring Vernier and one tunable delay-chain time amplifier (TA) are adopted. Both coarse and fine oscillators of the proposed Vernier which are designed by the same variable-resolution digital controlled oscillator can be switched off to decrease ground bounce during TA activities. With various control codes, the TDC resolution is also programmable. The test application-specified integrated circuit which has a 13-b resolution and occupies 0.02 mm(2) in TSMC 65-nm CMOS process can operate in either feedback or feedforward mode. In feedback mode, the measurements of sampling rate, resolution, input range, differential nonlinearity, and integral nonlinearity are 10 MHz, 0.98 ps, 5.76 ns, +/- 0.8 LSB, and +/- 2.2 LSB, respectively; it also consumes 3 mW at 1 V supply voltage. The sampling rate, resolution, and power dissipation of the feedforward operation are 250 MHz, 6.01 ps, and 17.5 mW, respectively. |
URI: | http://dx.doi.org/10.1109/TIE.2017.2669883 http://hdl.handle.net/11536/145509 |
ISSN: | 0278-0046 |
DOI: | 10.1109/TIE.2017.2669883 |
期刊: | IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS |
Volume: | 64 |
起始頁: | 4690 |
結束頁: | 4700 |
顯示於類別: | 期刊論文 |