標題: A Hardware-Efficient VLSI Architecture for Hybrid Sphere-MCMC Detection
作者: Yuan, Fang-Li
Yang, Chia-Hsiang
Markovic, Dejan
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-Jan-2011
摘要: This paper presents a hybrid soft-output MIMO detector that searches reliable soft-information in both deterministic and probabilistic ways. The fixed-complexity sphere detector (FSD) is first applied to provide near maximum-likelihood (ML) solutions. The solutions are next used to initialize the Markov Chain Monte Carlo (MCMC) detector that uses parallel Gibbs samplers (GSs) for remaining candidate enumeration. A lowcomplexity VLSI architecture is proposed to demonstrate the feasibility of hardware realization for high-throughput applications. Simulation results indicate that the hybrid detector has a 2.3x complexity reduction and a 2x throughput improvement compared to individual soft-output FSD and MCMC detectors.
URI: http://hdl.handle.net/11536/146317
ISSN: 1930-529X
期刊: 2011 IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE (GLOBECOM 2011)
Appears in Collections:Conferences Paper