標題: ESD Protection Design for High-Speed Applications in CMOS Technology
作者: Chen, Jie-Ting
Lin, Chun-Yu
Chang, Rong-Kun
Ker, Ming-Dou
Tzeng, Tzu-Chien
Lin, Tzu-Chiang
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-一月-2016
摘要: To prevent from electrostatic discharge (ESD) damages, the ESD protection design must be added on chip. The ESD protection design with low parasitic capacitance is needed for high-speed applications. In this work, an ESD protection design realized by stacked diodes with embedded silicon-controlled rectifier was proposed. Verified in silicon chip, the proposed ESD protection design with lower parasitic capacitance and higher ESD robustness was more suitable for high-speed ESD protection in CMOS technology.
URI: http://hdl.handle.net/11536/146687
ISSN: 1548-3746
期刊: 2016 IEEE 59TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS)
起始頁: 305
結束頁: 308
顯示於類別:會議論文