| 標題: | Latchup in Bulk FinFET Technology |
| 作者: | Dai, C. -T. Chen, S. -H. Linten, D. Scholz, M. Hellings, G. Boschke, R. Karp, J. Hart, M. Groeseneken, G. Ker, M. -D. Mocuta, A. Horiguchi, N. 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
| 關鍵字: | Latchup;bulk FinFET;silicon control rectifier (SCR) |
| 公開日期: | 1-一月-2017 |
| 摘要: | Latchup (LU) had been considered to be less important in advanced CMOS technologies. However, I/O interface and analog applications can still operate at high voltage (e.g., 1.8V or 3.3V) in sub-20nm bulk FinFET technologies. LU threats are never eliminated and the sensitivity towards LU is increased in bulk FinFET technology. |
| URI: | http://hdl.handle.net/11536/146847 |
| ISSN: | 1541-7026 |
| 期刊: | 2017 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) |
| 顯示於類別： | 會議論文 |
- Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technology / Chen, SH;Ker, MD
- Investigation of Unexpected Latchup Path Between HV-LDMOS and LV-CMOS in a 0.25-mu m 60-V/5-V BCD Technology / Dai, Chia-Tsen;Ker, Ming-Dou
- Dependence of device structures on latchup immunity in a high-voltage 40-V CMOS process with drain-extended MOSFETs / Hsu, Sheng-Fu;Ker, Ming-Dou
- Process and characteristics of modified Schottky barrier (MSB) p-channel FinFETs / Tsui, BY;Lin, CP
- Optimization Design on Active Guard Ring to Improve Latch-Up Immunity of CMOS Integrated Circuits / Chen, Chun-Cheng;Ker, Ming-Dou
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