Latchup in Bulk FinFET Technology

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Dai, C. -T.	en_US
dc.contributor.author	Chen, S. -H.	en_US
dc.contributor.author	Linten, D.	en_US
dc.contributor.author	Scholz, M.	en_US
dc.contributor.author	Hellings, G.	en_US
dc.contributor.author	Boschke, R.	en_US
dc.contributor.author	Karp, J.	en_US
dc.contributor.author	Hart, M.	en_US
dc.contributor.author	Groeseneken, G.	en_US
dc.contributor.author	Ker, M. -D.	en_US
dc.contributor.author	Mocuta, A.	en_US
dc.contributor.author	Horiguchi, N.	en_US
dc.date.accessioned	2018-08-21T05:56:56Z	-
dc.date.available	2018-08-21T05:56:56Z	-
dc.date.issued	2017-01-01	en_US
dc.identifier.issn	1541-7026	en_US
dc.identifier.uri	http://hdl.handle.net/11536/146847	-
dc.description.abstract	Latchup (LU) had been considered to be less important in advanced CMOS technologies. However, I/O interface and analog applications can still operate at high voltage (e.g., 1.8V or 3.3V) in sub-20nm bulk FinFET technologies. LU threats are never eliminated and the sensitivity towards LU is increased in bulk FinFET technology.	en_US
dc.language.iso	en_US	en_US
dc.subject	Latchup	en_US
dc.subject	bulk FinFET	en_US
dc.subject	silicon control rectifier (SCR)	en_US
dc.title	Latchup in Bulk FinFET Technology	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2017 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS)	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000416068500116	en_US
顯示於類別：	會議論文