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dc.contributor.authorShen, Wen-Weien_US
dc.contributor.authorLin, Yu-Minen_US
dc.contributor.authorChang, Hsiang-Hungen_US
dc.contributor.authorKuo, Tzu-Yingen_US
dc.contributor.authorFu, Huan-Chunen_US
dc.contributor.authorLee, Yuan-Changen_US
dc.contributor.authorLee, Shu-Manen_US
dc.contributor.authorLin, Ang-Yingen_US
dc.contributor.authorHuang, Shin-Yien_US
dc.contributor.authorChang, Tao-Chihen_US
dc.contributor.authorLee, Alvinen_US
dc.contributor.authorSu, Jayen_US
dc.contributor.authorHuang, Baronen_US
dc.contributor.authorBai, Dongshunen_US
dc.contributor.authorLiu, Xiaoen_US
dc.contributor.authorChen, Kuan-Nengen_US
dc.date.accessioned2018-08-21T05:56:59Z-
dc.date.available2018-08-21T05:56:59Z-
dc.date.issued2017-01-01en_US
dc.identifier.issn0569-5503en_US
dc.identifier.urihttp://dx.doi.org/10.1109/ECTC.2017.262en_US
dc.identifier.urihttp://hdl.handle.net/11536/146895-
dc.description.abstractFan-out wafer-level-packaging (FO-WLP) technology is developed with the advantages of smaller package size, higher Input/Output (I/O) counts, lower cost, and better performance. In this study, the FO-WLP technology is applied to TSV-less inter-connection technology of 2.5D IC packaging and a novel RDL-first wafer level packaging is demonstrated. Firstly, a pre-coated laser release layer at the interface of RDL and carrier wafer is used for the separation of the reconfigured wafer and carrier wafer with laser de-bonding technology. Since release layer material is the key factor for de-bonding, these materials are evaluated to determine the quality. Test chips are flip-chip bonded onto a carrier wafer with 2 layers of RDL and passivation, following by wafer molding process. Wafers reveal a warp surface due to chemical material shrinkage and CTE mismatch during post mold curing. Warpage of molded wafer is needed to be optimized for equipment handling and the warpage characterization is collected to analyze by different processes. To examine the quality of the structure, electrical measurement is carried out and their respective results are presented.en_US
dc.language.isoen_USen_US
dc.subjectFan-out wafer level packagingen_US
dc.subjectFO-WLPen_US
dc.subjectTSV-less interconnectionen_US
dc.titleProcess Development and Material Characteristics of TSV-less Interconnection Technology for FOWLPen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/ECTC.2017.262en_US
dc.identifier.journal2017 IEEE 67TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2017)en_US
dc.citation.spage35en_US
dc.citation.epage40en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000424702000006en_US
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