完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chang, Chun-Yen | en_US |
dc.contributor.author | Fan, Chia-Chi | en_US |
dc.contributor.author | Liu, Chien | en_US |
dc.contributor.author | Chiu, Yu-Chien | en_US |
dc.contributor.author | Cheng, Chun-Hu | en_US |
dc.date.accessioned | 2018-08-21T05:57:08Z | - |
dc.date.available | 2018-08-21T05:57:08Z | - |
dc.date.issued | 2017-01-01 | en_US |
dc.identifier.issn | 2162-7541 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/147095 | - |
dc.description.abstract | This work experimentally demonstrated a one-transistor ferroelectric versatile memory with the multi-technique integration of negative-capacitance mechanism, ferroelectric polarization effect and metal-strained engineering. The negative-capacitance versatile memory featured a steep sub-60mV/dec subthreshold swing, fast 20-ns switching speed and long 1012 cycled endurance. We successfully demonstrated that the metal-gate-induced strain could help to improve ferroelectric phase transformation. The excellent endurance characteristics could be ascribed to efficient ferroelectric negative-capacitance switching under low program/erase voltages. | en_US |
dc.language.iso | en_US | en_US |
dc.title | High Speed Negative Capacitance Ferroelectric Memory | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2017 IEEE 12TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) | en_US |
dc.citation.spage | 1 | en_US |
dc.citation.epage | 5 | en_US |
dc.contributor.department | 電子物理學系 | zh_TW |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electrophysics | en_US |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000426983400001 | en_US |
顯示於類別: | 會議論文 |