標題: A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control
作者: Cheng, Cheng-Hsiang
Tsai, Ping-Yuan
Yang, Tzu-Yi
Cheng, Wan-Hsueh
Yen, Ting-Yang
Luo, Zhicong
Qian, Xin-Hong
Chen, Zhi-Xin
Lin, Tzu-Han
Chen, Wei-Hong
Chen, Wei-Ming
Liang, Sheng-Fu
Shaw, Fu-Zen
Chang, Cheng-Siu
Hsin, Yue-Loong
Lee, Chen-Yi
Ker, Ming-Dou
Wu, Chung-Yu
電子工程學系及電子研究所
生醫電子轉譯研究中心
Department of Electronics Engineering and Institute of Electronics
Biomedical Electronics Translational Research Center
關鍵字: Closed-loop seizure control;low-noise neural-signal amplifier;neuromodulation system-on-chip (SoC);wireless bidirectional data telemetry;wireless power transmission
公開日期: 1-Nov-2018
摘要: A 16-channel closed-loop neuromodulation system-on-chip (SoC) for human epileptic seizure control is proposed and designed. In the proposed SoC, a 16-channel neural-signal acquisition unit (NSAU), a biosignal processor (BSP), a 16-channel high-voltage-tolerant stimulator (HVTS), and wireless power and bidirectional data telemetry are designed. In the NSAU, the input protection circuit is used to prevent MOSFET from overstressing by the high-voltage stimulations. Hence, NSAUs can share electrodes with stimulators. The auto-reset chopper-stabilized capacitive-coupled instrumentation amplifiers (AR-CSCCIAs) are designed with the chopper-stabilized technique with a new offset reduction loop. The measured input-referred noise is 2.09 mu V-rms and the noise-efficiency factor (NEF) is 3.78. The entropy-and-spectrum seizure detection algorithm is implemented in the BSP with 0.76-s seizure detection latency and 97.8% detection accuracy. When the seizure onset is detected by the BSP, the HVTS with adaptive supply control delivers 0.5-3-mA biphasic current stimulation to suppress the seizure onset. The proposed SoC is powered wirelessly, and the bidirectional data telemetry is realized through the same pair of coils in 13.56 MHz. The downlink data rate is 211 Kb/s with the binary phase-shift keying (BPSK) modulation and a new BPSK demodulator. The uplink data rate is 106 Kb/s with the load-shift keying (LSK) modulation. The proposed SoC is fabricated in a 0.18-mu m CMOS technology and occupies 25 mm(2). Electrical tests have been performed to characterize the SoC performance. In vivo animal experiments using mini-pigs have been performed to successfully verify the closed-loop neuromodulation functions on epileptic seizure suppression.
URI: http://dx.doi.org/10.1109/JSSC.2018.2867293
http://hdl.handle.net/11536/148400
ISSN: 0018-9200
DOI: 10.1109/JSSC.2018.2867293
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 53
起始頁: 3314
結束頁: 3326
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