標題: Monolithic Low Noise and Low Zero-g Offset CMOS/MEMS Accelerometer Readout Scheme
作者: Liu, Yu-Sian
Wen, Kuei-Ann
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Accelerometer readout;low noise;low zero-g offset
公開日期: 1-Dec-2018
摘要: A monolithic low noise and low zero-g offset CMOS/MEMS accelerometer and readout scheme in standard 0.18 m CMOS mixed signal UMC process is presented. The low noise chopper architecture and telescopic topology is developed to achieve low noise. The experiments show noise floor is 421.70 g/Hz. The whole system has 470 mV/g sensitivity. The power consumption is about 1.67 mW. The zero-g trimming circuit reduces the offset from 1242.63 mg to 2.30 mg.
URI: http://dx.doi.org/10.3390/mi9120637
http://hdl.handle.net/11536/148681
ISSN: 2072-666X
DOI: 10.3390/mi9120637
期刊: MICROMACHINES
Volume: 9
Appears in Collections:Articles