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dc.contributor.authorChang, CYen_US
dc.contributor.authorLin, CWen_US
dc.date.accessioned2019-04-02T06:00:53Z-
dc.date.available2019-04-02T06:00:53Z-
dc.date.issued1996-12-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://dx.doi.org/10.1109/55.545774en_US
dc.identifier.urihttp://hdl.handle.net/11536/149382-
dc.description.abstractIn this study, we propose a novel device structure combined with conventional hydrogenated amorphous silicon (a-Si:H) for the source and drain regions and microcrystalline silicon (mu c-Si:H) for the channel region to obtain a high-performance thin-film transistor (TFT), This is a vertical a-Si:H offset structure used to suppress OFF-state current to a small value which is comparable to the conventional a-Si:H TFT's with a much higher drivability. The fabrication process is simple, low temperature (less than or equal to 300 degrees C), and low cost, with a potential for high reliability.en_US
dc.language.isoen_USen_US
dc.titleA high-performance thin-film transistor with a vertical offset structureen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/55.545774en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume17en_US
dc.citation.spage572en_US
dc.citation.epage574en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:A1996VX16300009en_US
dc.citation.woscount3en_US
Appears in Collections:Articles