An 8 Gbps Fast-Locked Automatic Gain Control for PAM Receiver

Abstract

An 8 Gbps automatic gain control (AGC) loop for PAM receiver is proposed. Incorporating digital intensive gain control scheme, the dynamic range of the variable gain amplifier is 22 dB with a resolution of 0.9 dB/step. The locking time of the AGC loop is less than 200 ns and independent of input amplitude. Fabricated in a 0.18 mu m CMOS technology, the chip size is 0.62 mm x 0.62 mm. The total power dissipation is 84 mW from a 1.8 V supply.