標題: An analytical grain-barrier height model and its characterization for intrinsic poly-Si thin-film transistor
作者: Chen, HL
Wu, CY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: GB states;grain-barrier height;grain size;intrinsic poly-Si TFT
公開日期: 1-Oct-1998
摘要: An analytical model for the grain-barrier height of the intrinsic poly-Si thin-film transistors (TFT's) is developed, in which the grain-barrier height for the applied gate voltage smaller than the threshold voltage is obtained by solving the charge neutrality equation and the grain-barrier height for the applied gate voltage larger than the threshold voltage is obtained by using the quasi-two-dimensional (2-D) method. Good agreements between experimental and simulation results are obtained for wide gate voltage range.
URI: http://dx.doi.org/10.1109/16.725260
http://hdl.handle.net/11536/150381
ISSN: 0018-9383
DOI: 10.1109/16.725260
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 45
起始頁: 2245
結束頁: 2247
Appears in Collections:Articles