標題: A CMOS 33-mW 100-MHz 80-dB SFDR sample-and-hold amplifier
作者: Hsu, CC
Wu, HT
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-一月-2003
摘要: A high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of precharging and output capacitor coupling can mitigate the stringent performance requirements for the opamp, resulting in low power dissipation. Implemented in a standard 0.25 mum CMOS technology, the SHA achieves 80 dB spurious-free dynamic range (SFDR) for a 1.8 Vpp output at 100 MHz Nyquist sampling rate. The SHA occupies a die area of 0.35 mm(2) and dissipates 33 mW from a single 2.5 V supply.
URI: http://dx.doi.org/10.1109/VLSIC.2003.1221222
http://hdl.handle.net/11536/150602
DOI: 10.1109/VLSIC.2003.1221222
期刊: 2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS
起始頁: 263
結束頁: 266
顯示於類別:會議論文