標題: Ultra-Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm CMOS Technology
作者: Altolaguirre, Federico A.
Ker, Ming-Dou
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-Jan-2013
摘要: The gate tunneling current impacts seriously on the power-rail ESD clamp circuit, causing a large leakage current through the MOS capacitor used in ESD detection. In this work, a novel technique is implemented to eliminate the gate leakage current through the MOS capacitor by using a couple of transistors to control the voltage drop across the RC delay in the ESD detection circuit. This circuit has been verified in a 65-nm CMOS technology, with a total leakage current of 165nA under 1V bias, at 25 degrees C, and a ESD robustness of 3kV HBM and 200V MM.
URI: http://hdl.handle.net/11536/150685
ISSN: 2474-2724
期刊: 2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT)
Appears in Collections:Conferences Paper