完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Hudec, Boris | en_US |
dc.contributor.author | Chang, Che-Chia | en_US |
dc.contributor.author | Wang, I-Ting | en_US |
dc.contributor.author | Frohlich, Karol | en_US |
dc.contributor.author | Hou, Tuo-Hung | en_US |
dc.date.accessioned | 2019-04-02T06:04:32Z | - |
dc.date.available | 2019-04-02T06:04:32Z | - |
dc.date.issued | 2018-01-01 | en_US |
dc.identifier.issn | 1944-9399 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/151045 | - |
dc.description.abstract | Storage-class memory, non-volatile, ultra-dense and lightning fast, may enable memory-driven computing to revolutionize the current architectures leading to an on-chip processing of vast amount of data. 3D vertical resistive random access memory (ReRAM) is a hot candidate for storage-class memory. In this talk we review current state-of-the-art works which offer promising solutions, utilizing either filamentary or non-filamentary ReRAM designs, including our own. We will discuss the pros and cons of different approaches and summarize the open problems, drawing possible solutions. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Three dimensional integration of ReRAMs | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2018 IEEE 18TH INTERNATIONAL CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO) | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000458785600131 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |