標題: | A 40 Gb/s PAM-4 Receiver with 2-Tap DFE Based on Automatically Non-Even Level Tracking |
作者: | Hung, Chia-Tse Huang, Yu-Ping Chen, Wei-Zen 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Pulse-amplitude modulaiton (PAM);continuous time linear equalizer (CTLE);decision-feedback equalizer (DFE);automatically non-even level tracking (ANLT);sign-sign least mean square (SS-LMS) |
公開日期: | 1-一月-2018 |
摘要: | A 40 Gbh PAM-4 receiver comprised of continuous-time linear equalizer (CTLE) and 2-tap decision-feedback equalizers (DFE) based on a novel level tracking circuit (ANLT) is proposed. A sign-sign LMS engine is embedded for the DFE and ANLT coefficients adaptation to accommodate different channel loss. The ANLT is capable of automatically tracking a non-evenly spaced PAM-4 signal, allowing the receiver to demodulate a distorted input with 2-bit flash ADCs. Fabricated in a TSMC 40nm CMOS technology, the whole receiver consumes 241.8 m1V at 40 Gb/s operation. Core area is 0.274mm(2). |
URI: | http://hdl.handle.net/11536/151099 |
期刊: | 2018 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC): PROCEEDINGS OF TECHNICAL PAPERS |
起始頁: | 213 |
結束頁: | 214 |
顯示於類別: | 會議論文 |