標題: 3DICE: 3D IC Cost Evaluation Based on Fast Tier Number Estimation
作者: Chan, Cheng-Chi
Yu, Yen-Ting
Jiang, Iris Hui-Ru
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: 3D IC;TSV;cost evaluation;partitioning
公開日期: 2011
摘要: During the billion transistor era, 3D stacking offers an attractive solution for the difficulties resulting from large-scale design complexities. Moreover, 3D stacking can benefit performance, power, bandwidth, footprint, and heterogeneous technology mixing. However, before adopting the 3D design strategy, this study seeks to understand how much cost is required to trade these benefits. This paper proposes a 3D IC cost evaluation framework based on fast tier number estimation Using a reformulated Rent's rule, this study efficiently determines the number k of tiers to minimize the through-silicon via count and then automatically partitions a gate-level netlist into k tiers to minimize the total cost. This study conducted experiments on eight industrial test cases to show cost efficiency and effectiveness. Moreover, results prove that the reformulated Rent's rule indicates a strong correlation between the tier number and through-silicon via usage.
URI: http://hdl.handle.net/11536/15110
ISBN: 978-1-61284-914-0
ISSN: 1948-3295
期刊: 2011 12TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED)
起始頁: 50
結束頁: 55
顯示於類別:會議論文