A High-Performance Low V(MIN) 55nm 512Kb Disturb-Free 8T SRAM with Adaptive VVSS Control

標題:	A High-Performance Low V(MIN) 55nm 512Kb Disturb-Free 8T SRAM with Adaptive VVSS Control
作者:	Yang, Hao-I Yang, Shih-Chi Hsia, Mao-Chih Lin, Yung-Wei Lin, Yi-Wei Chen, Chien-Hen Chang, Chi-Shin Lin, Geng-Cing Chen, Yin-Nien Chuang, Ching-Te Hwang, Wei Jou, Shyh-Jye Lien, Nan-Chun Li, Hung-Yu Lee, Kuen-Di Shih, Wei-Chiang Wu, Ya-Ping Lee, Wen-Ta Hsu, Chih-Chiang 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics
公開日期:	2011
摘要:	This paper describes a high-performance low V(MIN) SRAM with a disturb-free 8T cell. The SRAM utilizes single-ended buffer Read, and cross-point data-aware Write Word-Line structure with adaptive VVSS control to eliminate Read disturb and Half-Select disturb, thus facilitating bit-interleaving architecture and achieving low V(MIN). A 512Kb test chip is implemented in UMC 55nm Standard Performance (SP) CMOS technology. The measurement results demonstrate operating frequency of 943MHz at 1.2V VDD and 209MHz at 0.6V VDD.
URI:	http://hdl.handle.net/11536/15150
ISBN:	978-1-4577-1617-1
期刊:	2011 IEEE INTERNATIONAL SOC CONFERENCE (SOCC)
起始頁:	197
結束頁:	200
Appears in Collections:	Conferences Paper