Wafer-level Cu-Cu bonding technology

doi:10.1016/j.microrel.2011.04.016

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Tang, Ya-Sheng	en_US
dc.contributor.author	Chang, Yao-Jen	en_US
dc.contributor.author	Chen, Kuan-Neng	en_US
dc.date.accessioned	2014-12-08T15:21:23Z	-
dc.date.available	2014-12-08T15:21:23Z	-
dc.date.issued	2012-02-01	en_US
dc.identifier.issn	0026-2714	en_US
dc.identifier.uri	http://dx.doi.org/10.1016/j.microrel.2011.04.016	en_US
dc.identifier.uri	http://hdl.handle.net/11536/15219	-
dc.description.abstract	Semiconductor industry currently utilizes copper wafer bonding as one of key technologies for 3D integration. This review paper describes both science and technology of copper wafer bonding with regard to present applications. The classification of Cu bonding, bonding mechanisms, process developments, its microstructure evolution, as well as other characterizations are reviewed. Researches about patterned Cu bonding, future prospects, and 3D integration using Cu bonding are discussed in this paper. (C) 2011 Elsevier Ltd. All rights reserved.	en_US
dc.language.iso	en_US	en_US
dc.title	Wafer-level Cu-Cu bonding technology	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1016/j.microrel.2011.04.016	en_US
dc.identifier.journal	MICROELECTRONICS RELIABILITY	en_US
dc.citation.volume	52	en_US
dc.citation.issue	2	en_US
dc.citation.spage	312	en_US
dc.citation.epage	320	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000300190600003	-
dc.citation.woscount	10	-
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