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dc.contributor.authorYu, M. H.en_US
dc.contributor.authorWang, L. T.en_US
dc.contributor.authorHuang, T. C.en_US
dc.contributor.authorLee, T. L.en_US
dc.contributor.authorCheng, H. C.en_US
dc.date.accessioned2014-12-08T15:21:32Z-
dc.date.available2014-12-08T15:21:32Z-
dc.date.issued2012en_US
dc.identifier.issn0013-4651en_US
dc.identifier.urihttp://hdl.handle.net/11536/15297-
dc.identifier.urihttp://dx.doi.org/10.1149/2.017203jesen_US
dc.description.abstractThe formation of the induced defects in the underlying Si substrate from the interaction of the partly relaxed source/drain strained-SiGe layer and subsequent millisecond annealing (MSA) have been systematically explored. It could be found that implantation in the shallower region of the strained-SiGe layer did not form defects in the underlying Si because the remaining strained-SiGe layer was sufficiently thick to resist wafer bending in response to the MSA thermal stress. However, deeper medium-level implantation indeed destroyed the part of the pseudomorphic strained-SiGe and the remaining strained-SiGe was too thin to withstand a significantly compressive stress induced by MSA surface heating and larger coefficient of thermal expansion (CTE) for SiGe than it for Si. Then brittle silicon substrate suffered a great tensile stress to generate numerous defects into plastic deformation. During MSA cooling, the over-bending of the surface SiGe layer contracted more than Si substrate and further results in highly tensile bending. Consequently, high defect density in the underlying Si results in high junction leakage and wafer bending leads to photolithographic limitation. A new approach for modifying the implantation conditions was developed to achieve a relaxation-less strained-SiGe layer and defect-free underlying Si substrate for the 32 nm PMOSFETs. (C) 2011 The Electrochemical Society. [DOI: 10.1149/2.017203jes] All rights reserved.en_US
dc.language.isoen_USen_US
dc.titleThe Strained-SiGe Relaxation Induced Underlying Si Defects Following the Millisecond Annealing for the 32 nm PMOSFETsen_US
dc.typeArticleen_US
dc.identifier.doi10.1149/2.017203jesen_US
dc.identifier.journalJOURNAL OF THE ELECTROCHEMICAL SOCIETYen_US
dc.citation.volume159en_US
dc.citation.issue3en_US
dc.citation.spageH243en_US
dc.citation.epageH249en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000299292100068-
dc.citation.woscount7-
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