標題: A 0.35-V 240-W Fast-Lock and Low-Phase-Noise Frequency Synthesizer for Implantable Biomedical Applications
作者: Wang, Shih-Hsing
Hung, Chung-Chih
電機資訊學士班
Undergraduate Honors Program of Electrical Engineering and Computer Science
關鍵字: Frequency synthesizers;Phase locked loops;Jitter;Voltage-controlled oscillators;Phase noise;Bandwidth;Power demand;Implantable applications;low power;MedRadio;PLL;ultra-low-power electronics;ultra low voltage
公開日期: 1-Dec-2019
摘要: For implantable frequency synthesizers, realizing ultra-low voltage (ULV) and low power in addition to meeting PLL targets, fast lock and low phase noise, poses a difficult challenge. This paper presents techniques to achieve PLL targets as well as ULV and low power in the same chip through the use of a regular CMOS technology node. A curvature-PFD technique achieves both faster locking and lower jitter compared with conventional techniques. A two-step switching technique substantially reduces the power consumption in current mirrors and reduce noise when switching from a charge pump. Leakage analysis and subthreshold-leakage-reduction technique reduce reference spur and jitter to the voltage-controlled oscillator (VCO). A dither technique randomizes and averages reference spurs. The proposed chip was implemented in 90-nm CMOS technology; the 0.35-V medical-band frequency synthesizer consumes 238-W power while generating output clock of 401.8 to 431.31-MHz and exhibiting a phase noise of -105.7 dBc/Hz at 1-MHz frequency offset with 20 s locking time.
URI: http://dx.doi.org/10.1109/TBCAS.2019.2941090
http://hdl.handle.net/11536/153544
ISSN: 1932-4545
DOI: 10.1109/TBCAS.2019.2941090
期刊: IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS
Volume: 13
Issue: 6
起始頁: 1759
結束頁: 1770
Appears in Collections:Articles