標題: Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter
作者: Sung, Po-Jung
Su, Chun-Jung
Lo, Shih-Hsuan
Hsueh, Fu-Kuo
Lu, Darsen D.
Lee, Yao-Jen
Chao, Tien-Sheng
電子物理學系
Department of Electrophysics
關鍵字: FeFET;forming gas annealing (FGA);steep slop;HfZrO2;ferroelectric
公開日期: 1-Jan-2020
摘要: In this study, ferroelectric FETs (FeFETs) and CMOS inverters are fabricated and analyzed, exhibiting 13% of 593 devices with sub-60 mV subthreshold swing (SS) at room temperature. Forming gas annealing (FGA) is found to not only enhance ferroelectricity but also significantly improve FeFET electrostatics. The experimental results indicate that FeFET with a narrow width shows weaker ferroelectric properties, and SS of sub-60 mV/dec with I-D change less than two orders of magnitude. However, FeFET with a broad channel width reveals stronger ferroelectric properties, and SS of sub-60 mV/dec is over 2 orders of magnitude of I-d. Finally, typical voltage transfer characteristics (VTCs) of a FeFET CMOS inverter with double sweeps at various V-D from 0.6 to 2 V are demonstrated. The results show that hysteresis in a FeFET CMOS inverter could have both clockwise (CW) and counter-clockwise (CCW) loops.
URI: http://dx.doi.org/10.1109/JEDS.2020.2987005
http://hdl.handle.net/11536/154592
ISSN: 2168-6734
DOI: 10.1109/JEDS.2020.2987005
期刊: IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY
Volume: 8
Issue: 1
起始頁: 474
結束頁: 480
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