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dc.contributor.authorNien, Yu-Tengen_US
dc.contributor.authorWu, Kai-Chiangen_US
dc.contributor.authorLee, Dong-Zhenen_US
dc.contributor.authorChen, Ying-Yenen_US
dc.contributor.authorChen, Po-Linen_US
dc.contributor.authorChern, Masonen_US
dc.contributor.authorLee, Jih-Nungen_US
dc.contributor.authorKao, Shu-Yien_US
dc.contributor.authorChao, Mango Chia-Tsoen_US
dc.date.accessioned2020-10-05T02:00:29Z-
dc.date.available2020-10-05T02:00:29Z-
dc.date.issued2019-01-01en_US
dc.identifier.isbn978-1-7281-4823-6en_US
dc.identifier.issn1089-3539en_US
dc.identifier.urihttp://hdl.handle.net/11536/155015-
dc.description.abstractIn order to reduce DPPM (defect parts per million), cell-aware (CA) methodology was proposed to cover various types of intra-cell defects. The resulting CA faults can be a 1-time-frame (ltf) or 2-time-frame (2tf) fault, and 2tf CA tests were experimentally verified to be capable of catching a significant number of defective parts not covered by other conventional tests. In this paper, we present a novel methodology for generating 2tf CA tests based on timing slack analysis. The proposed 2tf CA fault model, aware of timing slack and named TS, defines a fault (i) on a cell instance basis, and (ii) based on per-instance timing criticality (according to timing slack). More explicitly, for each cell instance with a specific defect injected, we check its output capacitive load and derive the corresponding extra delay. By comparing the extra delay against timing slack of the cell instance, a delay fault can be defined, and according to its severity, the fault can be further classified into small-delay fault or gross-delay fault. In contrast to prior 2tf CA methodology that is on a cell (rather than cell instance) basis and unaware of timing criticality/slack, our methodology can identify "more realistic" faults which really need to be considered, and potentially the cost/effort for testing those 2tf CA faults can be reduced. Experimental results on a set of 28nm industrial designs demonstrate that, due to more realistic fault identification, the numbers of identified small-delay faults and corresponding test patterns to be applied can be reduced by 35.1% and 24.1% respectively, leading to 40.7% reduction in the runtime of ATPG.en_US
dc.language.isoen_USen_US
dc.titleMethodology of Generating Timing-Slack-Based Cell-Aware Testsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2019 IEEE INTERNATIONAL TEST CONFERENCE (ITC)en_US
dc.citation.spage0en_US
dc.citation.epage0en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000540385000009en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper