Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Nien, Yu-Teng | en_US |
dc.contributor.author | Wu, Kai-Chiang | en_US |
dc.contributor.author | Lee, Dong-Zhen | en_US |
dc.contributor.author | Chen, Ying-Yen | en_US |
dc.contributor.author | Chen, Po-Lin | en_US |
dc.contributor.author | Chern, Mason | en_US |
dc.contributor.author | Lee, Jih-Nung | en_US |
dc.contributor.author | Kao, Shu-Yi | en_US |
dc.contributor.author | Chao, Mango Chia-Tso | en_US |
dc.date.accessioned | 2020-10-05T02:00:29Z | - |
dc.date.available | 2020-10-05T02:00:29Z | - |
dc.date.issued | 2019-01-01 | en_US |
dc.identifier.isbn | 978-1-7281-4823-6 | en_US |
dc.identifier.issn | 1089-3539 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/155015 | - |
dc.description.abstract | In order to reduce DPPM (defect parts per million), cell-aware (CA) methodology was proposed to cover various types of intra-cell defects. The resulting CA faults can be a 1-time-frame (ltf) or 2-time-frame (2tf) fault, and 2tf CA tests were experimentally verified to be capable of catching a significant number of defective parts not covered by other conventional tests. In this paper, we present a novel methodology for generating 2tf CA tests based on timing slack analysis. The proposed 2tf CA fault model, aware of timing slack and named TS, defines a fault (i) on a cell instance basis, and (ii) based on per-instance timing criticality (according to timing slack). More explicitly, for each cell instance with a specific defect injected, we check its output capacitive load and derive the corresponding extra delay. By comparing the extra delay against timing slack of the cell instance, a delay fault can be defined, and according to its severity, the fault can be further classified into small-delay fault or gross-delay fault. In contrast to prior 2tf CA methodology that is on a cell (rather than cell instance) basis and unaware of timing criticality/slack, our methodology can identify "more realistic" faults which really need to be considered, and potentially the cost/effort for testing those 2tf CA faults can be reduced. Experimental results on a set of 28nm industrial designs demonstrate that, due to more realistic fault identification, the numbers of identified small-delay faults and corresponding test patterns to be applied can be reduced by 35.1% and 24.1% respectively, leading to 40.7% reduction in the runtime of ATPG. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Methodology of Generating Timing-Slack-Based Cell-Aware Tests | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2019 IEEE INTERNATIONAL TEST CONFERENCE (ITC) | en_US |
dc.citation.spage | 0 | en_US |
dc.citation.epage | 0 | en_US |
dc.contributor.department | 資訊工程學系 | zh_TW |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Computer Science | en_US |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000540385000009 | en_US |
dc.citation.woscount | 0 | en_US |
Appears in Collections: | Conferences Paper |