單元識別及雙單元識別測試之產生方法

Abstract

本論文提出了一個新的故障模型來針對兩個標準單元間短路缺陷，並命名為雙單元識別故障模型。同時也展示了一個以佈局為基礎，用來自動化的從目標電路與標準單元庫中抽取有效的雙單元識別故障的方法。這些找出的雙單元識別故障可以輸出成商業自動測試圖案產生器支持的格式，以利於產生測試圖案。利用28奈米製程下的工業電路在自動測試圖案產生及故障模擬的結果展示出了雙單元識別故障並無法完全的被傳統故障模型涵蓋，包括固定型故障、轉態延遲故障、橋接故障與單元識別故障。因此雙單元識別故障需要一個獨特測試來偵測。

This thesis introduces a novel fault model, called the dual-cell-aware (DCA) fault model, which targets the short defects locating between two adjacent standard cells placed in the layout. A layout-based methodology is also presented to automatically extract valid DCA faults from targeted designs and cell libraries. The identified DCA faults are outputted in a format that can be applied to a commercial ATPG tool for test generation. The result of ATPG and fault simulation based on industrial designs under 28nm technology have demonstrated that the DCA faults cannot be fully covered by the tests of conventional fault models including stuck-at, transition, bridge and cell-aware faults and hence require their own designated tests to detect.