標題: | Abnormal hysteresis formation in hump region after positive gate bias stress in low-temperature poly-silicon thin film transistors |
作者: | Tu, Hong-Yi Chang, Ting-Chang Tsao, Yu-Ching Tai, Mao-Chou Tsai, Yu-Lin Huang, Shin-Ping Zheng, Yu-Zhe Wang, Yu-Xuan Lin, Chih-Chih Kuo, Chuan-Wei Tsai, Tsung-Ming Wu, Chia-Chuan Chien, Ya-Ting Huang, Hui-Chun 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | low-temperature polycrystalline-silicon thin-film transistor;dual sweep operation;abnormal hump;hysteresis |
公開日期: | 30-九月-2020 |
摘要: | Degradation in low-temperature polycrystalline-silicon thin-film transistors after electrical stress was thoroughly investigated in this work. Main channel degradation, abnormal hump generation and hysteresis appearing in the hump region can be observed after positive bias stress. Furthermore, the difference in subthreshold swing (SS) values between forward/reverse sweep is observed. The electron trapping into the gate insulator (GI) dominates the main degradation and the hump generation. Additionally, the difference in SS values which appears in the hump region is attributed to the interface traps and the hysteresis is caused by electron trapping/detrapping into GI. |
URI: | http://dx.doi.org/10.1088/1361-6463/ab9918 http://hdl.handle.net/11536/155202 |
ISSN: | 0022-3727 |
DOI: | 10.1088/1361-6463/ab9918 |
期刊: | JOURNAL OF PHYSICS D-APPLIED PHYSICS |
Volume: | 53 |
Issue: | 40 |
起始頁: | 0 |
結束頁: | 0 |
顯示於類別: | 期刊論文 |