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dc.contributor.authorSu, Pinen_US
dc.contributor.authorYou, Wei-Xiangen_US
dc.date.accessioned2020-10-05T02:01:28Z-
dc.date.available2020-10-05T02:01:28Z-
dc.date.issued2019-01-01en_US
dc.identifier.isbn978-1-7281-4031-5en_US
dc.identifier.issn2380-9248en_US
dc.identifier.urihttp://hdl.handle.net/11536/155246-
dc.description.abstractUsing an analytical subthreshold potential model, this paper shows that the negative-capacitance FinFET (NC-FinFET) inherently possesses a superior electrostatic integrity than the baseline FinFET. Taking into account the spacer induced distributed charges in our subthreshold model, we demonstrate that an adequate spacer design can be utilized to further enhance the NC effect and the electrostatic integrity for NC-FinFETs. This may serve as a way to extend the FinFET scaling.en_US
dc.language.isoen_USen_US
dc.titleElectrostatic Integrity in Negative-Capacitance FETs - A Subthreshold Modeling Approachen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2019 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)en_US
dc.citation.spage0en_US
dc.citation.epage0en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000553550000014en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper