完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Su, Pin | en_US |
dc.contributor.author | You, Wei-Xiang | en_US |
dc.date.accessioned | 2020-10-05T02:01:28Z | - |
dc.date.available | 2020-10-05T02:01:28Z | - |
dc.date.issued | 2019-01-01 | en_US |
dc.identifier.isbn | 978-1-7281-4031-5 | en_US |
dc.identifier.issn | 2380-9248 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/155246 | - |
dc.description.abstract | Using an analytical subthreshold potential model, this paper shows that the negative-capacitance FinFET (NC-FinFET) inherently possesses a superior electrostatic integrity than the baseline FinFET. Taking into account the spacer induced distributed charges in our subthreshold model, we demonstrate that an adequate spacer design can be utilized to further enhance the NC effect and the electrostatic integrity for NC-FinFETs. This may serve as a way to extend the FinFET scaling. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Electrostatic Integrity in Negative-Capacitance FETs - A Subthreshold Modeling Approach | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2019 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | en_US |
dc.citation.spage | 0 | en_US |
dc.citation.epage | 0 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000553550000014 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |