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dc.contributor.authorWu, Kai-Chiangen_US
dc.contributor.authorHuang, Wei-Taoen_US
dc.contributor.authorHuang, Chiao-Yangen_US
dc.date.accessioned2020-10-05T02:01:30Z-
dc.date.available2020-10-05T02:01:30Z-
dc.date.issued2019-01-01en_US
dc.identifier.isbn978-1-7281-2490-2en_US
dc.identifier.issn1942-9398en_US
dc.identifier.urihttp://hdl.handle.net/11536/155273-
dc.description.abstractDevice aging, which causes significant loss on circuit performance and lifetime, has been a primary factor in reliability degradation of nanoscale designs. In this paper, we propose to exploit timing speculation for aging resilience, based on deploying Razor flip-flops. By formulating the problem based on Boolean satisfiability, we can determine the optimal deployment of Razor flip-flops, such that maximum degree of aging resilience can be achieved in a cost-effective manner. Experimental results show that more than 50% of aging-induced performance degradation can be recovered, while reducing the number of required Razor flip-flops by more than 3X, as compared to the case of naive Razor flip-flop deployment.en_US
dc.language.isoen_USen_US
dc.subjectaging resilienceen_US
dc.subjectBoolean satisfiabilityen_US
dc.subjectRazor flip-flopen_US
dc.titleICE-RADAR: In-situ, Cost-Effective Razor Flip-Flop Deployment for Aging Resilienceen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2019 IEEE 25TH INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS 2019)en_US
dc.citation.spage263en_US
dc.citation.epage268en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000555813100059en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper