Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Wu, Kai-Chiang | en_US |
dc.contributor.author | Huang, Wei-Tao | en_US |
dc.contributor.author | Huang, Chiao-Yang | en_US |
dc.date.accessioned | 2020-10-05T02:01:30Z | - |
dc.date.available | 2020-10-05T02:01:30Z | - |
dc.date.issued | 2019-01-01 | en_US |
dc.identifier.isbn | 978-1-7281-2490-2 | en_US |
dc.identifier.issn | 1942-9398 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/155273 | - |
dc.description.abstract | Device aging, which causes significant loss on circuit performance and lifetime, has been a primary factor in reliability degradation of nanoscale designs. In this paper, we propose to exploit timing speculation for aging resilience, based on deploying Razor flip-flops. By formulating the problem based on Boolean satisfiability, we can determine the optimal deployment of Razor flip-flops, such that maximum degree of aging resilience can be achieved in a cost-effective manner. Experimental results show that more than 50% of aging-induced performance degradation can be recovered, while reducing the number of required Razor flip-flops by more than 3X, as compared to the case of naive Razor flip-flop deployment. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | aging resilience | en_US |
dc.subject | Boolean satisfiability | en_US |
dc.subject | Razor flip-flop | en_US |
dc.title | ICE-RADAR: In-situ, Cost-Effective Razor Flip-Flop Deployment for Aging Resilience | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2019 IEEE 25TH INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS 2019) | en_US |
dc.citation.spage | 263 | en_US |
dc.citation.epage | 268 | en_US |
dc.contributor.department | 資訊工程學系 | zh_TW |
dc.contributor.department | Department of Computer Science | en_US |
dc.identifier.wosnumber | WOS:000555813100059 | en_US |
dc.citation.woscount | 0 | en_US |
Appears in Collections: | Conferences Paper |