標題: Logical Effort Model Extension with Temperature and Voltage Variations
作者: Wu, Chun-Hui
Lin, Shun-Hua
Chiueh, Herming
電信工程研究所
Institute of Communications Engineering
公開日期: 2008
摘要: The method of "Logical Effort Delay Model" allows designers to quickly estimate delay time and optimize logic paths. But the previous variances of logical effort models do not mention how to handle process, voltage, and temperature (PVT) variations appropriately, which may induce a serious misestimate. According to simulation results, delay time increases 21% while temperature increasing from 0 C to 125 C, and increases 2X while supply voltage decreasing from IV to 0.5V in 90nm process. Thus a simple linear extended logical effort g, I/g=(m(t)t+b(t))V(DD)+C, supporting for temperature t and supply voltage V(DD) variations is presented. The proposed model enables designers to estimate the logic path delay and to optimize an N-stage logic network under different temperature and supply voltage conditions. After validation, the accuracy of this new extended logical effort model can achieve about 90%.
URI: http://hdl.handle.net/11536/1586
ISBN: 978-1-4244-3365-0
期刊: 14TH INTERNATIONAL WORKSHOP ON THERMAL INVESTIGATION OF ICS AND SYSTEMS
起始頁: 85
結束頁: 88
Appears in Collections:Conferences Paper