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dc.contributor.authorChen, Kun-Mingen_US
dc.contributor.authorHuang, Guo-Weien_US
dc.contributor.authorChen, Bo-Yuanen_US
dc.contributor.authorChiu, Chia-Sungen_US
dc.contributor.authorHsiao, Chih-Huaen_US
dc.contributor.authorLiao, Wen-Shiangen_US
dc.contributor.authorChen, Ming-Yien_US
dc.contributor.authorYang, Yu-Chien_US
dc.contributor.authorWang, Kai-Lien_US
dc.contributor.authorLiu, Chee Weeen_US
dc.date.accessioned2014-12-08T15:22:45Z-
dc.date.available2014-12-08T15:22:45Z-
dc.date.issued2012-04-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://hdl.handle.net/11536/16080-
dc.description.abstractThe effects of mechanical stress on the dc and high-frequency performances of laterally diffused MOS (LDMOS) transistors with different layout structures were investigated by using the wafer bending method. A 3.1% peak cutoff frequency (f(T)) enhancement is achieved for the multifinger device under 0.051% biaxial tensile strain. For LDMOS with annular layout, the f(T) enhancement is increased to 3.7% due to the various channel directions. Our results suggest the strain technology can be adopted in LDMOS for RF applications. The transconductance and gate capacitance were also extracted to clearly demonstrate the f(T) variations.en_US
dc.language.isoen_USen_US
dc.subjectAnnular layouten_US
dc.subjectbiaxial tensile strainen_US
dc.subjectcutoff frequencyen_US
dc.subjectlaterally diffused MOS (LDMOS)en_US
dc.subjectmechanical stressen_US
dc.titleLDMOS Transistor High-Frequency Performance Enhancements by Strainen_US
dc.typeArticleen_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume33en_US
dc.citation.issue4en_US
dc.citation.epage471en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000302232900002-
dc.citation.woscount0-
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