橫向擴散的射頻金氧半場效電晶體之佈局設計與熱特性分析

Abstract

近年來，射頻橫向擴散金氧半場效電晶體(RF LDMOS)已廣泛地應用在手機基地台中，作為功率放大器的主要元件。為了能因應新一代通訊標準的需求，LDMOS的特性必須不斷的加以改進。在本論文中，我們將探討兩種結構：ring 和fishbone的直流、高頻和射頻功率特性。在fishbone結構中，我們設計了具有不同漂移(drift)區長度、閘極長度、閘極指根數目與結構單元數目的元件。其中，具有較短漂移區長度的元件雖有較小的崩潰電壓，但其直流、高頻特性以及線性度均比較長漂移區長度的元件來的好。為了得到較低的開啟態電阻(on-resistance)以及緊密的排列結構，我們採用了一種四邊形的ring結構。在傳統的MOSFET中，寄生汲極電容指的是n+的汲極和p型基底間的接面電容。因此，汲極通常擺在內側來降低寄生電容。而在LDMOS的元件中，寄生電容指的是deep n-well (DNW)和p型基底間的接面電容。所以汲極擺在外側的結構並不會提高汲極電容。再者，由於ring結構排列較fishbone緊密，使得DNW的面積減小，汲極電容降低。為了能更進一步了解元件參數對高頻特性的影響，我們以小訊號等效電路將其參數萃出作為分析比較。實驗結果顯示，ring結構之所以有較佳的特性是由於其寄生的汲極電阻比fishbone來的小。在ring結構中，汲極擺在閘極外側能有效的增加汲極面積，降低汲極電阻，進而達到降低元件開啟態電阻的目的。我們所設計的ring結構可以在相同的崩潰電壓基礎下降低開啟態電阻，並將最大震盪頻率(fmax) 提升24.5%。此外輸出功率、功率增益以及附加功率效率均有較佳的表現，而線性度則和fishbone結構不相上下。由於ring結構只更動光罩之設計，製程流程並無改變，因此實為一大優點。 由於功率元件深受溫度的影響，因此元件的溫度效應也將一並討論。由之前的實驗結果得知，LDMOS有較大的的寄生汲極電阻。因此需扣除寄生電阻的影響才能得到正確的溫度引起之fT變化對轉導變化的關係。ring結構由於排列較的較緊密，因此有較大的熱阻和較小的熱容，也就是自我熱效應比fishbone嚴重。在脈衝量測下，不論直流還是高頻特性均顯示ring有較好的特性。因此若是在脈衝模式操作下，ring結構將會有更佳的特性表現。 另一方面，元件的電容特性也有完整的分析。由於LDMOS的通道為非均勻參雜且具有漂移區，因此電容會有峰值產生。而在較大的汲極偏壓下，我們首次發現ring結構的電容會出現第二個峰值。這是因為ring結構的轉角處電流密度較小，使得閘極需偏壓在較大的電壓下才會進入類飽和。藉由溫度的變化來研究電容的改變，我們發現電容主要是受到臨限電壓、類飽和電流和漂移區的空乏電容所影響。因此在建立電容模型時，必須將這些效應考慮進去，以提升模擬的準確度。此外，根據實驗的結果來選擇電容對溫度較不敏感的偏壓區域對於電路的設計也極為重要。

RF LDMOS is nowadays widely used for base station applications. To meet the demands imposed by new communication standards, the performance of LDMOS is subject to continuous improvements. In this thesis, two types of layout structures, ring and fishbone, were studied for DC, high-frequency, and RF power characteristics. For fishbone structures, variation of drift lengths and channel widths, different numbers of gate fingers and cells were investigated. The structure with smaller LDrift has better on-resistance, fT, fmax, and linearity, but smaller breakdown voltage. To achieve lower on-resistance and a more compact device size, we adopted a “ring” structure in the layout design. In the traditional design, drain inside was usually used to lower the parasitic drain capacitance. For MOSFET, the conventional parasitic drain capacitance refers to the n+ drain to p-substrate junction capacitance. Hence, the drain was always surrounded by the transistor channel and source to reduce the area. In LDMOS, however, the parasitic drain capacitance refers to the deep n-well (DNW) to p-substrate junction capacitance. Therefore, drain capacitance would not increase in a drain outside structure. Since the ring has more compact device size the area of DNW is smaller than the fishbone. This smaller area leads to a lower drain capacitance in the ring structure. In order to determine the effect of device parameters on high-frequency characteristics more clearly, small-signal equivalent circuit was built to be analyzed. From the simulation results, the smaller drain parasitic resistance in the ring could be the key factor for improving fT and fmax. For having the drift region, drain parasitic resistance is larger in the LDMOS than in the MOSFET and become an important parameter. In the ring structure, drain outside design has an advantage over drain inside in having larger area for output terminal. The extra areas in the corner would have lowered the drain parasitic resistance and improve the on-resistance. By using the ring structure, higher drain current and transconductance were shown by the reason of larger equivalent W/L and lower drain parasitic resistance. Also, fmax were enhanced by about 24.5% due to the lower drain parasitic resistance. As for microwave power characteristics, output power, power gain and power added efficiency (PAE) were improved with a similar linearity compared to the fishbone. Its reveals that the ring structure had a better performance and similar breakdown voltage compared to the fishbone structure, without altering the process flow. For high-power applications, temperature is an important issue. For conventional MOS transistors in RF applications, the temperature effect was investigated by studying the temperature dependence of fT, which is proportional to the transconductance. Owing to the higher drain resistance in the LDMOS transistors, the fT is also affected by drain resistance. By de-embedding the effect of drain resistance, we show the real relation between the temperature-induced variation of fT and transconductance. In order to study the self-heating effect on the performance of LDMOS, I-V and RF characteristics were also measured under a pulsed condition. From the extracted thermal resistance and thermal capacitance, the effect of self-heating was more severe in ring structure. In the pulsed-mode measurement, the ring has better drain current, fT and fmax than the fishbone structure. Although the ring structure showed lower static drain current than the fishbone structure at high gate biases due to the significant self-heating effect, its current drive capability could be improved using a pulsed-mode operation. In another part of this thesis, we discussed and analyzed the capacitance characteristics completely. For having a non-uniform doping channel and the existence of the drift region, CGS+ CGB and CGD exhibit a peak in LDMOS. In the ring structure, the second peaks in a capacitance-voltage curve have been observed at high drain voltages for the first time. While the corner region of the drift in the ring shows lower current density than the edge region, it needs higher gate voltage to enter quasi-saturation. By increasing the gate voltage, the current in the corner region is high enough to make the velocity of electrons in the drift saturated. Therefore, the corner operates in quasi-saturation and second peaks are generated. The thermal effects on capacitances were also investigated. Because the capacitances are affected mainly by the threshold voltage, quasi-saturation current and drift depletion capacitance, the variation of the capacitances with temperature is more complicated than that in conventional MOSFET, and it depends on the bias condition. Based on the result we analyzed, we can well model the temperature-dependence capacitance by adding these parameters and also can choose a bias condition with lower temperature sensitivity in capacitances.