標題: On Constructing Low Power and Robust Clock Tree via Slew Budgeting
作者: Chang, Yeh-Chi
Wang, Chun-Kai
Chen, Hung-Ming
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: clock synthesis;slew
公開日期: 2012
摘要: Clock skew resulted by process variation becomes more and more serious as technology shrinks. In 2010, ISPD held a high performance clock network synthesis contest; it considered supply-voltage variation and wire manufacturing variation. Previous works show that the main issue of variation induced skew is on supply-voltage variation. To trade off power and supply-voltage variation induced skew more effectively, we adapt a tree topology which use a timing model independent symmetrical tree at top level to drive the bottom level non-symmetry trees. Our method gives top tree more power budget to reduce supply-voltage variation induced skew and greedily saves power consuming in bottom level. Experimental results are evaluated from the benchmarks of ISPD contest 2010. Compared with state-of-the-art cross link work, the proposed technique reduces 10% of power consumption on average and also improves the run time.
URI: http://hdl.handle.net/11536/16231
ISBN: 978-1-4503-1167-0
期刊: ISPD 12: PROCEEDINGS OF THE 2012 INTERNATIONAL SYMPOSIUM ON PHYSICAL DESIGN
結束頁: 129
Appears in Collections:Conferences Paper