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dc.contributor.authorHan, Ming-Hungen_US
dc.contributor.authorChen, Hung-Binen_US
dc.contributor.authorChang, Chia-Jungen_US
dc.contributor.authorWu, Jia-Jiunen_US
dc.contributor.authorChen, Wen-Chongen_US
dc.contributor.authorTsai, Chi-Chongen_US
dc.contributor.authorChang, Chun-Yenen_US
dc.date.accessioned2014-12-08T15:23:18Z-
dc.date.available2014-12-08T15:23:18Z-
dc.date.issued2012-04-01en_US
dc.identifier.issn0021-4922en_US
dc.identifier.urihttp://dx.doi.org/04DP04en_US
dc.identifier.urihttp://hdl.handle.net/11536/16354-
dc.description.abstractIn this work, double reduced surface field (RESURF) laterally diffused metal oxide semiconductor (LDMOS) device combines a new implant technology without using additional mask in standard 0.18 mu m technology has been proposed and successfully fabricated. The breakdown voltage (BV) can be improved significantly with simply changing the implanted region length in this implant technology. Firstly, hydrodynamic transport simulations which analyze the high bias condition electric field distributions are examined to predict and explain the increase of breakdown voltage. Then the fabricated devices process flow is demonstrated, the structures are performed, and the breakdown voltages increase with different n-type double diffusion (NDD) photoresistor (PR) size using the change of PR exposure dose are investigated. The measurement results show that maximum NDD PR size achieves BV improvement of 6.3%, and 5% increase of figure of merit (FOM) evaluation. Throughout the whole fabrication process, no additional mask and device area show the potential of cost effective with the proposed technique. Such devices with good off-state breakdown voltage and specific on-resistance are very competitive with similar technologies and show good promising in system on chip (SOC) applications. (C) 2012 The Japan Society of Applied Physicsen_US
dc.language.isoen_USen_US
dc.titleA Novel Cost Effective Double Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor Design for Improving Off-State Breakdown Voltageen_US
dc.typeArticleen_US
dc.identifier.doi04DP04en_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICSen_US
dc.citation.volume51en_US
dc.citation.issue4en_US
dc.citation.epageen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000303928600103-
dc.citation.woscount2-
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