Improvement on ESD Robustness of Lateral DMOS in High-Voltage CMOS ICs by Body Current Injection

Abstract

With the waffle layout style, body-injected technique implemented by body current injection on n-channel lateral DMOS (nLDMOS) has been successfully verified in a 0.5-mu m 16-V BCD process. The TIP measured results confirmed that the secondary breakdown current (I(t2)) of waffle nLDMOS can be significantly increased by the body current injection with the corresponding trigger circuit design. The latchup immunity of power-rail ESD protection circuit can be further improved by the stacked configuration with multiple nLDMOS devices in HV ICs.