標題: Pipelined Arithmetic Encoder Design for Lossless JPEG XR Encoder
作者: Chien, Ching-Yen
Huang, Sheng-Chieh
Pan, Chia-Ho
Fang, Ce-Min
Chen, Liang-Gee
電控工程研究所
Institute of Electrical and Control Engineering
關鍵字: JPEG XR;HD-Photo;encoder;ASIC
公開日期: 2009
摘要: With rapid progress of sensors, display devices, and computing engines, image application exists everywhere. High quality, high compression rates of digital image and low computational cost are important factors of consumer electronics. In this paper, we proposed a 4:4:4 lossless JPEG XR encoder design. In JPEG XR encoder, entropy coding is a critical module of encoder. We proposed a well-defined timing schedule of pipeline architecture to speed up the entropy encoding, which is the most computationally intensive part in JPEG XR encoder. This design can be used for the digital photography applications to achieve the low complexity of computation, low storage, and high dynamic range.
URI: http://hdl.handle.net/11536/16585
ISBN: 978-1-4244-2975-2
期刊: ISCE: 2009 IEEE 13TH INTERNATIONAL SYMPOSIUM ON CONSUMER ELECTRONICS, VOLS 1 AND 2
起始頁: 859
結束頁: 862
Appears in Collections:Conferences Paper