| 標題: | UNIFIED ARRAY ARCHITECTURE FOR DISCRETE COSINE TRANSFORM, SINE TRANSFORM AND THEIR INVERSES |
| 作者: | GUO, JI CHEN, CS JEN, CW 電控工程研究所 Institute of Electrical and Control Engineering |
| 關鍵字: | DISCRETE COSINE TRANSFORMS;SINE TRANSFORMS;SYSTOLIC ARRAYS |
| 公開日期: | 12-Oct-1995 |
| 摘要: | A unified array design for the discrete cosine transform, discrete sine transform and their inverses based on a new general formulation is presented. The presented design provides the flexibility to adaptively select different types of transforms in transform coding according to the characteristics of images for minimising the bit rate as much as possible. |
| URI: | http://dx.doi.org/10.1049/el:19951254 http://hdl.handle.net/11536/1700 |
| ISSN: | 0013-5194 |
| DOI: | 10.1049/el:19951254 |
| 期刊: | ELECTRONICS LETTERS |
| Volume: | 31 |
| Issue: | 21 |
| 起始頁: | 1811 |
| 結束頁: | 1812 |
| Appears in Collections: | Articles |
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- A NEW ARRAY ARCHITECTURE FOR PRIME-LENGTH DISCRETE COSINE TRANSFORM / GUO, JI;LIU, CM;JEN, CW
- Hardware-efficient DFT designs with cyclic convolution and subexpression sharing / Chang, TS;Guo, JI;Jen, CW
- A NOVEL CORDIC-BASED ARRAY ARCHITECTURE FOR THE MULTIDIMENSIONAL DISCRETE HARTLEY TRANSFORM / GUO, JI;LIU, CM;JEN, CW
- ON THE DESIGN OF VLSI ARRAYS FOR DISCRETE FOURIER-TRANSFORM / LIU, CM;JEN, CW
- A memory-efficient realization of cyclic convolution and its application to discrete cosine transform / Chen, HC;Guo, JI;Chang, TS;Jen, CW
- THE EFFICIENT MEMORY-BASED VLSI ARRAY DESIGNS FOR DFT AND DCT / GUO, JI;LIU, CM;JEN, CW
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