標題: An Intelligent Analysis of Iddq Data for Chip Classification in Very Deep-Submicron (VDSM) CMOS Technology
作者: Chang, Chia-Ling (Lynn)
Chang, Chia-Ching (Austin)
Chan, Hui-Ling
Wen, Charles H. -P.
Bhadra, Jayanta
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2012
摘要: Iddq testing has been a critical integral component in test suites for screening unreliable devices. As the silicon technology keeps shrinking, Iddq values and their variation increase as well. Moreover, along with rapid design scaling, defect-induced leakage currents become less significant when compared to full-chip current and also make themselves less distinguishable. Traditional Iddq methods become less effective and cause more test escapes and yield loss. Therefore, in this paper, a new test method named sigma-Iddq testing is proposed and integrates (1) a variation-aware full-chip leakage estimator and (2) a clustering algorithm to classify chip without using threshold values. Experimental result shows that sigma-Iddq testing achieves a higher classification accuracy in a 45nm technology when compared to a single-threshold Iddq testing. As a result, both the process-variation and design-scaling impacts are successfully excluded and thus the defective chips can be identified intelligently.
URI: http://hdl.handle.net/11536/17013
ISBN: 978-1-4673-0772-7
ISSN: 2153-6961
期刊: 2012 17TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC)
起始頁: 163
結束頁: 168
Appears in Collections:Conferences Paper