完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Kao, Yao-Huang | en_US |
dc.contributor.author | Hsieh, Yi-Bin | en_US |
dc.date.accessioned | 2014-12-08T15:24:39Z | - |
dc.date.available | 2014-12-08T15:24:39Z | - |
dc.date.issued | 2006 | en_US |
dc.identifier.isbn | 978-1-4244-0172-7 | en_US |
dc.identifier.issn | 1548-3746 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/17122 | - |
dc.description.abstract | A fully integrated spread spectrum clock generator (SSCG) using the VCO direct modulation was presented. The dual-path loop filter in the phased locked loop was employed to reduce the required area of capacitance in the filter by using another charge pump circuit. In the meantime, the third charge pump was used to achieve the triangle modulation. The proposed circuit had been fabricated by TSMC 0.35um CMOS single-poly quadruple-metal process. The clock rate from 50MHz to 480MHz with center spread spectrum ratios with 0.5%-2% was verified. The size of chip area was 0.82xO.8mm(2) including the loop filter and the power consumption was 27.5mW at 400MHz. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A fully integrated spread spectrum clock generator using a dual-path loop filter | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | IEEE MWSCAS'06: Proceedings of the 2006 49th Midwest Symposium on Circuits and Systems, Vol II | en_US |
dc.citation.spage | 7 | en_US |
dc.citation.epage | 10 | en_US |
dc.contributor.department | 傳播研究所 | zh_TW |
dc.contributor.department | Institute of Communication Studies | en_US |
dc.identifier.wosnumber | WOS:000249557100002 | - |
顯示於類別: | 會議論文 |