完整後設資料紀錄
DC 欄位語言
dc.contributor.authorKao, Yao-Huangen_US
dc.contributor.authorHsieh, Yi-Binen_US
dc.date.accessioned2014-12-08T15:24:39Z-
dc.date.available2014-12-08T15:24:39Z-
dc.date.issued2006en_US
dc.identifier.isbn978-1-4244-0172-7en_US
dc.identifier.issn1548-3746en_US
dc.identifier.urihttp://hdl.handle.net/11536/17122-
dc.description.abstractA fully integrated spread spectrum clock generator (SSCG) using the VCO direct modulation was presented. The dual-path loop filter in the phased locked loop was employed to reduce the required area of capacitance in the filter by using another charge pump circuit. In the meantime, the third charge pump was used to achieve the triangle modulation. The proposed circuit had been fabricated by TSMC 0.35um CMOS single-poly quadruple-metal process. The clock rate from 50MHz to 480MHz with center spread spectrum ratios with 0.5%-2% was verified. The size of chip area was 0.82xO.8mm(2) including the loop filter and the power consumption was 27.5mW at 400MHz.en_US
dc.language.isoen_USen_US
dc.titleA fully integrated spread spectrum clock generator using a dual-path loop filteren_US
dc.typeProceedings Paperen_US
dc.identifier.journalIEEE MWSCAS'06: Proceedings of the 2006 49th Midwest Symposium on Circuits and Systems, Vol IIen_US
dc.citation.spage7en_US
dc.citation.epage10en_US
dc.contributor.department傳播研究所zh_TW
dc.contributor.departmentInstitute of Communication Studiesen_US
dc.identifier.wosnumberWOS:000249557100002-
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