標題: | A fully integrated spread-spectrum clock generator by using direct VCO modulation |
作者: | Hsieh, Yi-Bin Kao, Yao-Huang 傳播研究所 Institute of Communication Studies |
關鍵字: | phase-locked loop (PLL);spread-spectrum clock generator (SSCG) |
公開日期: | 1-八月-2008 |
摘要: | A compact architecture for a fully-integrated spread-spectrum clock generator (SSCG) using voltage-controlled oscillator direct modulation is presented in this paper. A dual-path loop filter in the phase-locked loop is employed to reduce the size of the capacitance in the filter with the aid of an extra charge pump and a unity gain amplifier. At the same time, a third-charge pump which generates triangular waves is used to perform the function of a spread-spectrum. The proposed circuit has been fabricated using a 0.35-mu m CMOS single-poly quadruple-metal process. The clock rate from 50 to 480 MHz with a center spread range of between 0.5 % and 2 % are verified and are close to the theoretical analyses. The size of the chip area is 0.82 x 0.8 mm(2) (including the loop filter) and the power consumption was 27.5 mW at 400 MHz. Index Terms-Phase-locked loop (PLL), spread-spectrum clock generator (SSCG). |
URI: | http://dx.doi.org/10.1109/TCSI.2008.918194 http://hdl.handle.net/11536/8496 |
ISSN: | 1549-8328 |
DOI: | 10.1109/TCSI.2008.918194 |
期刊: | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS |
Volume: | 55 |
Issue: | 7 |
起始頁: | 1845 |
結束頁: | 1853 |
顯示於類別: | 期刊論文 |