A CMOS 15-bit 125-MS/s time-interleaved ADC with digital background. calibration

doi:10.1109/CICC.2006.320912

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DC 欄位	值	語言
dc.contributor.author	Lee, Zwei-Mei	en_US
dc.contributor.author	Wang, Cheng-Yeh	en_US
dc.contributor.author	Wu, Jieh-Tsorng	en_US
dc.date.accessioned	2014-12-08T15:24:43Z	-
dc.date.available	2014-12-08T15:24:43Z	-
dc.date.issued	2006	en_US
dc.identifier.isbn	1-4244-0075-9	en_US
dc.identifier.uri	http://hdl.handle.net/11536/17157	-
dc.identifier.uri	http://dx.doi.org/10.1109/CICC.2006.320912	en_US
dc.description.abstract	A 15-bit 125-MS/s two-channel time-interleaved pipelined ADC is fabricated in a 0.18 mu m CMOS technology, and achieves 91.9 dB SFDR, 69.9 dB SNDR for a 9.99 MHz input. The ADC uses a single sample-and-hold amplifier which employs a precharging circuit technique to mitigate the performance requirements for its opamp. Digital background calibration is applied to maintain the conversion linearity of each AID channel and also correct both gain and offset mismatches between the two channels. Excluding I/O buffers, the chip occupies an area of 4.3 x 4.3 mm(2) and dissipates 909 mW from a 1.8 V supply.	en_US
dc.language.iso	en_US	en_US
dc.title	A CMOS 15-bit 125-MS/s time-interleaved ADC with digital background. calibration	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.doi	10.1109/CICC.2006.320912	en_US
dc.identifier.journal	PROCEEDINGS OF THE IEEE 2006 CUSTOM INTEGRATED CIRCUITS CONFERENCE	en_US
dc.citation.spage	209	en_US
dc.citation.epage	212	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000243380700044	-
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