A 3.1 similar to 10.6 GHz CMOS direct-conversion receiver for UWB applications

Abstract

In this paper, a 3.1 similar to 10.6 GHz fully integrated low-power CMOS direct-conversion receiver for ultra-wideband (UWB) applications is proposed and analyzed. The proposed receiver consists of a wideband low-noise amplifier (WLNA), quadrature down-conversion mixers, output I/Q buffers and a carrier generator. This chip was designed in 0.13-um CMOS technology. According to the simulation results, the proposed receiver has noise figure (NF) of 4.1 similar to 7.1 dB, receiver voltage gain of 22 dB, and input-referred 1-dB compression point (P-1dB) of -22 similar to-26 dBm and third-order intercept point (IIP3) of -12 similar to-16 dBm. It consumes 38.4 mW from 1.2 V power supply.