完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Su, Wei-Li | en_US |
dc.contributor.author | Chiueh, Herming | en_US |
dc.contributor.author | Huang, Po-Tsang | en_US |
dc.contributor.author | Hwnag, Wei | en_US |
dc.date.accessioned | 2014-12-08T15:25:03Z | - |
dc.date.available | 2014-12-08T15:25:03Z | - |
dc.date.issued | 2006 | en_US |
dc.identifier.isbn | 978-1-4244-0394-3 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/17420 | - |
dc.identifier.uri | http://dx.doi.org/10.1109/ICECS.2006.379848 | en_US |
dc.description.abstract | A low power pulsed edge-triggered latch based on the static edge-triggered latch (ETL) is presented for survivor memory (SMU) unit of Viterbi decoder for low power high speed wireless local area network (WLAN) applications. By reducing clock loading and transistor number, the proposed low swing static ETL has less clock loading, smaller cell area and power-delay product compared to traditional master-slave register. Moreover, a stage-reduced SMU is introduced later for saving both area and power consumption. The proposed low swing static ETL and stage-reduced SMU are designed and simulated in TSMC 0.13um standard CMOS process, and the operating clock frequency is at 1GHz. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A low power pulsed edge-triggered latch for survivor memory unit of Viterbi decoder | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.doi | 10.1109/ICECS.2006.379848 | en_US |
dc.identifier.journal | 2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3 | en_US |
dc.citation.spage | 553 | en_US |
dc.citation.epage | 556 | en_US |
dc.contributor.department | 電信工程研究所 | zh_TW |
dc.contributor.department | Institute of Communications Engineering | en_US |
dc.identifier.wosnumber | WOS:000252489600138 | - |
顯示於類別: | 會議論文 |