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dc.contributor.authorSun, YuChenen_US
dc.contributor.authorHuang, ChingYaoen_US
dc.date.accessioned2014-12-08T15:25:04Z-
dc.date.available2014-12-08T15:25:04Z-
dc.date.issued2006en_US
dc.identifier.isbn978-1-4244-0386-8en_US
dc.identifier.urihttp://hdl.handle.net/11536/17448-
dc.description.abstractThis paper introduces a development and validation platform that combines hardware modeling and communication system simulation. This platform enables the use of a single platform for multiple purposes throughout a communication system design, including system simulation, software development and hardware modeling. Besides providing cycle accuracy hardware model, the platform is integrated with a multi-device simulation environment. Based on the platform, designers could complete protocol analysis and system simulation in a single stage. The platform is useful for the designs of communication components whose behaviors are highly coupled with transmission medium and other parallel components. In this paper, we will present the basic components and their design strategies.en_US
dc.language.isoen_USen_US
dc.titleA development and validation platform for communication SOC designen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2006 IEEE Asia Pacific Conference on Circuits and Systemsen_US
dc.citation.spage101en_US
dc.citation.epage104en_US
dc.contributor.department電機學院zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000246793200026-
Appears in Collections:Conferences Paper