完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Tseng, Sheng-Che | en_US |
dc.contributor.author | Meng, Chinchun | en_US |
dc.contributor.author | Li, Shao-Yu | en_US |
dc.contributor.author | Su, Jen-Yi | en_US |
dc.contributor.author | Huang, Guo-Wei | en_US |
dc.date.accessioned | 2014-12-08T15:25:19Z | - |
dc.date.available | 2014-12-08T15:25:19Z | - |
dc.date.issued | 2005 | en_US |
dc.identifier.isbn | 0-7803-9433-X | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/17699 | - |
dc.description.abstract | This paper demonstrates a low-cost 2.4 GHz single-ended frequency divider with the divide-by-value from 256 to 271 in standard 0.35-um 2P4M CMOS technology. This frequency divider is composed of a synchronous CML divide-by4/5 prescaler, an asynchronous TSPC TFF divide-by-64 divider and digital control circuitry. This proposed divider is single-ended and compatible to the single-ended low-phase-noise Colpitts VCO. The operating frequency range of the divider is from 400 MHz to 2.9 GHz. Most of input sensitivity levels are about -10 dBm and the lowest level is -25 dBm at 2.4 GHz. Its core power consumption is about 28 mW. The chip size is 1.20.7 mm(2). | en_US |
dc.language.iso | en_US | en_US |
dc.subject | prescaler | en_US |
dc.subject | CMOS | en_US |
dc.subject | single-ended | en_US |
dc.subject | current mode logic | en_US |
dc.subject | divide-by-4/5 | en_US |
dc.title | .2.4 GHz divide-by-256 similar to 271 single-ended frequency divider in standard 0.35-mu m CMOS technology | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2005 ASIA-PACIFIC MICROWAVE CONFERENCE PROCEEDINGS, VOLS 1-5 | en_US |
dc.citation.spage | 856 | en_US |
dc.citation.epage | 859 | en_US |
dc.contributor.department | 電信工程研究所 | zh_TW |
dc.contributor.department | Institute of Communications Engineering | en_US |
dc.identifier.wosnumber | WOS:000237449901043 | - |
顯示於類別: | 會議論文 |