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dc.contributor.authorTseng, Sheng-Cheen_US
dc.contributor.authorMeng, Chinchunen_US
dc.contributor.authorLi, Shao-Yuen_US
dc.contributor.authorSu, Jen-Yien_US
dc.contributor.authorHuang, Guo-Weien_US
dc.date.accessioned2014-12-08T15:25:19Z-
dc.date.available2014-12-08T15:25:19Z-
dc.date.issued2005en_US
dc.identifier.isbn0-7803-9433-Xen_US
dc.identifier.urihttp://hdl.handle.net/11536/17699-
dc.description.abstractThis paper demonstrates a low-cost 2.4 GHz single-ended frequency divider with the divide-by-value from 256 to 271 in standard 0.35-um 2P4M CMOS technology. This frequency divider is composed of a synchronous CML divide-by4/5 prescaler, an asynchronous TSPC TFF divide-by-64 divider and digital control circuitry. This proposed divider is single-ended and compatible to the single-ended low-phase-noise Colpitts VCO. The operating frequency range of the divider is from 400 MHz to 2.9 GHz. Most of input sensitivity levels are about -10 dBm and the lowest level is -25 dBm at 2.4 GHz. Its core power consumption is about 28 mW. The chip size is 1.20.7 mm(2).en_US
dc.language.isoen_USen_US
dc.subjectprescaleren_US
dc.subjectCMOSen_US
dc.subjectsingle-endeden_US
dc.subjectcurrent mode logicen_US
dc.subjectdivide-by-4/5en_US
dc.title.2.4 GHz divide-by-256 similar to 271 single-ended frequency divider in standard 0.35-mu m CMOS technologyen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2005 ASIA-PACIFIC MICROWAVE CONFERENCE PROCEEDINGS, VOLS 1-5en_US
dc.citation.spage856en_US
dc.citation.epage859en_US
dc.contributor.department電信工程研究所zh_TW
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.identifier.wosnumberWOS:000237449901043-
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