A novel design of high-speed divide-by-3/4 counter for a dual-modulus prescaler

Abstract

A novel design for a high-speed divide-by-3/4 counter is presented. The proposed design reduces not only the critical path delay but also the feedback path delay, hence it can increase the operating speed. With this divide-by-3/4 counter, a divide-by-127/128 dual-modulus prescaler (DMP), implemented in 0.18 mu m CMOS technology, shows a maximum operating frequency of 7.0 GHz with 2.4mW power consumption at 1.8V supply voltage, which has 25% speed improvement and still consumes less power as well compared to the recently-reported one.