完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Yang, Hao-I | en_US |
dc.contributor.author | Chuang, Ching-Te | en_US |
dc.contributor.author | Hwang, Wei | en_US |
dc.date.accessioned | 2014-12-08T15:25:19Z | - |
dc.date.available | 2014-12-08T15:25:19Z | - |
dc.date.issued | 2009 | en_US |
dc.identifier.isbn | 978-1-4244-2933-2 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/17702 | - |
dc.description.abstract | This paper presents a detailed analysis on the impacts of various gate-oxide breakdown (BD) paths in column-based header- and footer-gated SRAMs. It is shown that with gate-oxide BD, the RSNM (Read Static Noise Margin) degrades, while the WM (Write Margin) improves in general. The effects of gate-to-source BD of cell transistors are shown to confine to the individual cell, while multiple cells suffering cell transistor drain-to-drain BD in a column could cumulatively affect VVDD (header structure) or VVSS (footer structure), thus influencing other cells in the same column. In particular, we show that the gate-oxide BD of the power-switches have server and even detrimental effects on the margin, stability, and performance of the SRAM array | en_US |
dc.language.iso | en_US | en_US |
dc.subject | gate-oxide breakdown | en_US |
dc.subject | power gating technology | en_US |
dc.subject | SRAM | en_US |
dc.title | Impact of Gate-Oxide Breakdown on Power-Gated SRAM | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2009 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS | en_US |
dc.citation.spage | 93 | en_US |
dc.citation.epage | 96 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000270582500024 | - |
顯示於類別: | 會議論文 |