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dc.contributor.authorKer, MDen_US
dc.contributor.authorHsu, SFen_US
dc.date.accessioned2014-12-08T15:25:22Z-
dc.date.available2014-12-08T15:25:22Z-
dc.date.issued2005en_US
dc.identifier.isbn0-7803-8803-8en_US
dc.identifier.urihttp://hdl.handle.net/11536/17744-
dc.description.abstractAn efficient measurement setup for transient-induced latchup (TLU) with bi-polar trigger is evaluated in this paper. The influences of the current-blocking diode and the current-limiting resistance on TLU immunity are investigated with the silicon controlled rectifier (SCR) fabricated in a 0.25-mu m CMOS technology. The measurement setup without a current-blocking diode but with a small current-limiting resistance is recommended to evaluate TLU immunity of CMOS ICs. This recommended measurement setup not only can accurately judge the TLU level of CMOS ICs without over estimation, but also is beneficial to avoid electrical over-stress (EOS) damage on device under test (DUT). To further prove the utility of this recommended TLU measurement in the real circuits, a ring oscillator fabricated by 0.25-mu m CMOS technology is used as the test circuit for verification.en_US
dc.language.isoen_USen_US
dc.titleEvaluation on efficient measurement setup for transient-induced latchup with bi-polar triggeren_US
dc.typeProceedings Paperen_US
dc.identifier.journal2005 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 43RD ANNUALen_US
dc.citation.spage121en_US
dc.citation.epage128en_US
dc.contributor.department電機學院zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000230058000020-
Appears in Collections:Conferences Paper