Evaluation on efficient measurement setup for transient-induced latchup with bi-polar trigger

Abstract

An efficient measurement setup for transient-induced latchup (TLU) with bi-polar trigger is evaluated in this paper. The influences of the current-blocking diode and the current-limiting resistance on TLU immunity are investigated with the silicon controlled rectifier (SCR) fabricated in a 0.25-mu m CMOS technology. The measurement setup without a current-blocking diode but with a small current-limiting resistance is recommended to evaluate TLU immunity of CMOS ICs. This recommended measurement setup not only can accurately judge the TLU level of CMOS ICs without over estimation, but also is beneficial to avoid electrical over-stress (EOS) damage on device under test (DUT). To further prove the utility of this recommended TLU measurement in the real circuits, a ring oscillator fabricated by 0.25-mu m CMOS technology is used as the test circuit for verification.