標題: | Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs |
作者: | Jiang, TY Liu, CNJ Jou, JY 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2005 |
摘要: | Debugging priority is a helpful technique to assist debugging faulty HDL designs [9]. However, debugging priority obtained by sorting confidence score is not good enough due to the inaccuracy in estimating likelihood of correctness for error candidates. Therefore, we developed Refined Confidence Score for deriving better debugging priority. |
URI: | http://hdl.handle.net/11536/17798 |
ISBN: | 0-7803-8834-8 |
ISSN: | 0271-4302 |
期刊: | 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS |
起始頁: | 5682 |
結束頁: | 5685 |
顯示於類別: | 會議論文 |