Full metadata record
DC FieldValueLanguage
dc.contributor.authorKao, HLen_US
dc.contributor.authorChin, Aen_US
dc.contributor.authorLai, JMen_US
dc.contributor.authorLee, CFen_US
dc.contributor.authorChiang, KCen_US
dc.contributor.authorMcAlister, SPen_US
dc.date.accessioned2014-12-08T15:25:25Z-
dc.date.available2014-12-08T15:25:25Z-
dc.date.issued2005en_US
dc.identifier.isbn0-7803-8983-2en_US
dc.identifier.issn1529-2517en_US
dc.identifier.urihttp://hdl.handle.net/11536/17813-
dc.description.abstractA novel microstrip line layout is developed to direct measure the min. noise figure (NFmin) accurately instead of the complicated de-embedding procedure in conventional CPW line. Very low NFmin of 1.05 dB at 10 GHz is directly measured in 16 gate fingers 0.18 mu m MOSFETs without any de-embedding. Based on the accurate NFmin measurement, we have developed the self-consistent DC, S-parameters and NFmin model to predict device characteristics after the continuous stress with good accuracy.en_US
dc.language.isoen_USen_US
dc.subjectNFminen_US
dc.subjectRF noiseen_US
dc.subjectlifetimeen_US
dc.subjectstressen_US
dc.subjectmodelen_US
dc.titleModeling RF MOSFETs after electrical stress using low-noise microstrip line layouten_US
dc.typeProceedings Paperen_US
dc.identifier.journal2005 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Digest of Papersen_US
dc.citation.spage157en_US
dc.citation.epage160en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000230541500035-
Appears in Collections:Conferences Paper